Embodiments of the invention relate to a semiconductor device and a method of manufacturing the same.
FIG. 1 is a perspective view of a power transistor.
Referring to FIG. 1, a first conductive drain area (N+ junction) 11, a first conductive epitaxial layer (N-epi) 12 formed on the drain area 11 and a second conductive silicon layer (P-sub) 13 formed on the epitaxial layer 12 are formed in a semiconductor substrate 10. Here, the first and second conductive types may respectively mean N-type and P-type, or vice versa.
A transistor having a vertical structure is formed on the semiconductor substrate 10. To this end, a plurality of trenches are formed by removing the drain area 11 and a portion of the epitaxial layer 12 in the semiconductor substrate 10. A plurality of gate electrodes 15, each having an oxide layer 14 and a polysilicon gate (the hatched part of electrode 15), are formed in the plurality of trenches.
Source areas 16 doped with first conductive impurity ions are formed in the second conductive silicon layer 13 at opposed sides of each gate electrode 15.
Since power loss of such a power transistor must be reduced, it is important to reduce on-state resistance. An epitaxial wafer (epiwafer) is used to lower the on-state resistance, and a transistor having a vertical structure is formed. Further, a plurality of gate electrodes 15 are formed, and the length of the gate electrode 15 is sufficiently long to reduce the resistance sufficiently.
Meanwhile, the transistor is maintained in an off state. When a positive (+) voltage is applied to the gate electrode 15, a channel is formed in a vertical direction in the silicon layer 13 (P-sub) between the source and drain areas 16 and 11. Thus, a current flows through the channel in the vertical direction. That is, in the transistor, a positive (+) voltage must be always applied to the gate electrode 15 such that an on state is maintained.
Accordingly, embodiments of the invention relate to a semiconductor device (e.g., a power transistor), in which a power control state can be stored, and power can be applied in accordance with the power control state.
In addition, embodiments of the invention provide a semiconductor device used as a switch for power control, in which a power control state can be stored without applying additional control power.
According to an aspect of the embodiment, there is provided a semiconductor device, which includes a semiconductor substrate having source and drain areas; a floating gate between the source and drain areas which may have a programmed or erased state, thereby controlling a current flow between the source and drain areas in accordance with the state of the floating gate; and a tunneling gate adapted to program and/or erase the floating gate.
According to another aspect of the invention, there is provided a semiconductor device, which includes a semiconductor substrate having a first conductive type drain area, a second conductive type silicon layer thereon and a first conductive type source area thereon (e.g., in a vertical direction); floating gates formed in a plurality of trenches in the source area and the silicon layer; an insulating layer on an outer surface of the floating gate; a tunneling gate on the floating gates; and sidewalls on opposite sides of the floating gate.
According to still another aspect of the invention, there is provided a method of manufacturing a semiconductor device, which includes the steps of forming a floating gate having a portion in a semiconductor substrate; forming an oxide layer on an entire surface of the semiconductor substrate; forming a tunneling gate on the floating gate; and implanting first conductive impurity ions into the semiconductor substrate, thereby forming a source area, and forming a drain area beneath the semiconductor substrate.